1. Field
The present disclosure relates generally to processing systems, and more specifically, to systems and techniques for transferring data between slave devices in response to a single bus command from a bus mastering device.
2. Background
At the heart of most modem processing systems is a communications structure referred to as a bus. The bus moves information between various processing entities in the system. Today, most on-chip bus architectures are fairly standardized. These standardized bus architectures typically have independent and separate read, write and address channels.
This type of bus architecture is often found in processing systems with one or more general purpose processors supported by memory. In these systems, memory provides a storage medium that holds the programs and data needed by the processors to perform their functions. A processor may read or write to the memory by placing an address on the address channel and sending the appropriate read/write control signal. Depending on the state of the read/write control, the processor either writes to the memory over the write channel or reads from the memory over the read channel.
In some processing systems, there may be a need to transfer data between memory devices. By way of example, a processor may need to transfer data from memory to a transceiver for transmission over a network. This data transfer operation requires a two-step process. First, the processor must read the data from memory. Next, the processor must send the data to the transceiver. Accordingly, there is a need in the art for techniques that allow data to be efficiently transferred between two devices in a processing system without having to pass it through the processor.